About the Author:
Daniel Bogaerts, a distinguished electromechanical engineer who graduated from the Free University of Brussels, spearheaded R&D innovations at Philips, where he spent a few years developing switch-mode power supplies and performing advanced particle accelerator development at Ion Beam Applications. Now, as of 2022, he's a sought-after consultant in switch-mode power converters and all related aspects of electronic design, including control and EMC.
Point-of-load switching converters are nowadays ubiquitous on PCBs, as various supply voltages are often required by different parts of the circuitry while the board itself is generally powered by a single source. Compared to linear regulators, switching PoLs provide significantly higher efficiency, and they can generate output voltages that are higher than the input voltage. Being switchers, these converters intrinsically generate sharp current and voltage slopes, emitting broadband noise which may affect the board's functional performance as well as its compliance with EMC standards. Better understanding of the noise emission mechanisms leads to simple though sometimes counter-intuitive layout design rules that can greatly reduce the EMC issues of switching PoLs.
This article discusses the principles of PoL converters and introduces issues that affect electromagnetic compatibility (EMC). Good practices for PoL design are explained.
Traditionally, a buck converter is represented as shown below; the diagram is straightforward, and its operation is easy to explain:
In the steady state, the average output voltage Vo = Vi × (Ton/T), where Ton is the ON time of the switch and T is the cycle period. This is true regardless of the output current (provided it is high enough to never drop to zero during the OFF time of the switch). The output capacitor filters out the current ripple in the inductor to provide a stable voltage at the output.
For simulation purposes, we’ll first modify the schematic:
In our example, the buck converter is stepping the voltage down from a 5 V source to 3.3 V supply rail.
The switch is replaced by a pulsed voltage source (Vswitch) in series with the quasi-ideal diode Ds. When the pulse voltage is zero, the switch is ON; when the pulse voltage is 5 V, the diode does not conduct and the switch is OFF. This is a simple way to actuate the switch while controlling its rate of voltage change so as to reproduce the behavior of a physical MOSFET transistor, whose dV/dt is limited by the Miller effect.
We will use a high switching frequency (1 MHz) with transition times equal to 1% of the cycle period (i.e., 10 ns). We will also assume that the output capacitor is perfect and of infinite capacitance, such that we can replace it with the voltage source Vo.
Finally, using the initial condition “.ic” directive, we will make the converter operate at an output current of approximately 3 A.
Launching the simulation, we can check that we get the expected near-perfect behavior, with the current in the inductor rising when the input voltage is applied, and decreasing during the freewheeling phase:
Simulations are nice, but they always neglect some part of real life. Let’s consider the ground connection between the input voltage source Vi (in practice, the input capacitor) and the freewheeling diode D. It will most often be implemented as a ground plane in an internal layer, but even so some impedance will be present. Let’s introduce into this connection the very small value of 1 nH, which roughly corresponds to the inductance of a 1 mm–long wire:
Let's launch the simulation:
The waveforms are almost unchanged, which is not surprising, since 1 nH is a very small value. But let’s have a look at the voltage difference between the input and output grounds (in practice, the lower-voltage terminals of the input and output capacitors):
Something is going on there; let’s zoom in:
The oscillations that we observe in the plot above are very fast, with a period that is half the minimum step size specified in the .tran simulation directive (0.1 ns); we are probably missing something. Let’s see if we can get closer to reality by adding another “parasitic” component to the circuit. One obvious candidate is the parasitic capacitance of the diode, as it can come into action precisely at that moment (it was previously shorted by the diode conducting):
The shape of the signal has changed, but its amplitude has not decreased.
Zooming in again:
This looks much more like a physical signal, resembling a damped sinusoid with a period of about 2 ns (20 times the minimum simulation step). This should not come as a surprise, as the resonant frequency of the LC circuit made of L_GND and Cd is 1/(2π×√(1 nH x 100 pF)) = 503 MHz: we are quite close.
Let’s pause and do the following two things:
First, let’s find the root cause of this behavior and, to that end, let’s have a look at the current through L_GND:
Zooming in:
We see a very sharp rise of the current—in a few nanoseconds—from zero to the value of the output current. That’s quite logical: as soon as the switch starts conducting, diode D, which was carrying freewheeling output current, becomes reverse-biased and switches off, so the output current, “pushed” by the main choke L, suddenly has no other path than to return to the negative side of Vi through the parasitic inductance L_GND.
Now remember the basic law governing the voltage across an inductor:
V = L dI/dt
The L in this formula is proportional to the area enclosed by the loop in which the fast current variation flows, i.e., the loop formed by the source capacitor Vi, the switch, and the freewheeling diode D. The formula shows that the magnitude of the issue is proportional to this inductance, thus to this area, hence the first design rule:
Rule #1: Minimize the area enclosed by the loop formed by the input capacitor, the switch, and the freewheeling diode.
Second, consider this: even a very small inductance causes a high-frequency voltage with peak values around 1.5 V to appear across the ground connection between the input and the output of the buck converter, and thus also between the GND pins of ICs and other components on the board. This is large enough to cause nasty functional issues, especially with fast, low-level signals. It is also large enough to generate external EMC issues between, for example, connectors and cables connected to different parts of the circuit, and thus to different grounds from a high-frequency perspective.
What can we do about it? The answer is: not much, but…
The first thing that comes to mind is to slow down the rate of rise of the current through the switch. We can do this, but it will come at the cost of increased switching losses in the switch—and there will still be some voltage ringing across L_GND, though with reduced amplitude.
A second idea would be to dampen the oscillation, which can be achieved by adding an RC circuit in parallel with the resonating capacitor, i.e., diode D in the present case.
The rule of thumb is simple: the added capacitor must be significantly larger than the resonating one, say five times, and the resistor can be approximated as ½√(L/C), thus in this case Cam = 500 pF and Ram = 1.6 Ω.
In practice, the values of parasitic circuit elements are not known precisely, but they can be determined experimentally, and the values of Cam and Ram can then be calculated as explained above.
This will not come completely for free, however, as, on top of the additional components themselves, the energy exchanged at every switching cycle of the transistor will be dissipated in the damping resistor; in this case, P = Cam × Vi² × f = 500 pF × 25 V² × 1 MHz = 12.5 mW. This is generally acceptable for a 10 W converter, as it degrades its efficiency by only around 0.1%.
Let’s try this:
As we can see, the damping has done its job, so it was a good idea … but the initial voltage spike remains stubbornly in place and may still cause disturbances in the circuitry around the converter.
There is actually a very simple solution for eliminating this effect without any additional components; let’s consider this slightly modified circuit:
The change we are concerned with here is the horizontal wire connection at the bottom of the circuit. We have not changed anything in the PCB netlist, as the parasitic inductor L_GND, being parasitic, is not part of it, but now there is obviously no voltage spike anymore between the negative terminal of the input “capacitor” Vi and that of the output “capacitor” Vo. This remains true even if we add a parasitic inductor L_GND2 in this path:
There is still some voltage between the two nodes, but we are now in the mV range, so this is much less likely to wreak havoc in the rest of the board.
We can thus formulate our second design rule:
Rule #2: Connect the negative terminal of the output capacitor directly to the negative terminal of the input capacitor; route separately the anode of the freewheeling diode to the negative terminal of the input capacitor; strictly avoid any common section between these two paths.
Now imagine that, according to Rule #2, we have routed that critical track on, say, the top PCB layer. Following good practice, we’ll naturally use one of the internal layers, say, the second, as a continuous ground plane and connect the GND pins of all ICs and other devices to it.
Planar transformers use PCB tracks as windings, one layer holding the primary and another the secondary winding. Like any transformer, their functional principle is current cancellation: when current is flowing in one winding, another current will flow in the opposite direction in the other coupled winding to cancel the magnetic field created by the first.
The windings of a transformer usually have multiple turns, but the same principle applies to windings with a single turn.
And that’s exactly what we have done with our critical loop on the top layer and a ground plane on the second layer; the latter is just a transformer secondary, short-circuited.
Back to our model: this effect can easily be simulated by introducing a coupling factor between L_GND and L_GND2.
A coupling factor of 0.95 corresponds to a leakage inductance of about 10%—thus not an excessively tight coupling.
Let’s launch the simulation and again check the voltage between the two “ground” nodes:
Well, it looks as if we are back to square one…
Having a ground plane under the critical loop is actually a good idea, because it greatly helps to avoid spatial expansion of both the moderate AC electrical field caused by the swinging voltage on the “ac” node, and, more importantly, of the magnetic field caused by the fast current variation. It comes, however, at the cost of having approximately the same current variation circulating through the ground plane.
Same cause, same cure:
Rule #3: Create a ground plane under the critical loop consisting of the input capacitor, the switch, and the freewheeling diode; however, make this part of the ground plane an “island,” connected to the rest of the ground plane only at one point, preferably at the negative terminal of the input capacitor.
This means also that the negative terminal of the output capacitor must be connected to the “general” ground plane and not to this “island.” By doing so, we can revert to our previous model without coupling between the parasitic inductances.
Note also that the shielding effect of the ground plane is not perfect, partly because it is not a perfect short circuit at high frequencies because of the skin effect, which reduces the effective copper thickness (6.5 µm at 100 MHz, 2 µm at 1 GHz) and thus increases its resistance. It is thus good practice to avoid running sensitive signal tracks on other layers beneath the critical loop.
No component is ideal, and the filtering inductor L is no exception. It is generally a wound component, where the proximity of multiple wires create a parasitic parallel capacitance whose value will vary with the geometry and the manufacturing process.
Let’s assume a value of 50 pF and look at what happens:
This time we get damped oscillations around 700 MHz on both switch ON and switch OFF events, with an amplitude an order of magnitude smaller than the one seen previously, but still large enough to create issues.
Where does it come from? The voltage on node “ac” is basically a square wave, and we have an LC circuit consisting of the main inductor parasitic capacitance C_L that we just introduced and the small inductor L_GND2. Let’s check its resonant frequency:
1/(2π×√LC) = 1/(2π×√(10–9 × 50×10–12) = 712 MHz: again, close enough.
How can this situation be improved?
A first guideline is to be careful when selecting the main inductor L; opt for a component with the lowest possible capacitance. This will certainly help, but some capacitance will inevitably remain.
A more radical solution is to make the L_GND2 inductance as low as possible, and this is easy to do. Just move the output capacitor against the input capacitor, connecting their negative terminals together as tightly as possible:
By doing this, we have moved the voltage oscillation to the other side of L_GND2, and it does not appear anymore between the GND on the input side and the GND on the output side, as they are now one and the same node as far as can be achieved.
Hence:
Rule #4: Move the input and the output capacitors as close to each other as possible; connect their negative terminals together as tightly as possible.
This article explained important design considerations for switch-mode power supplies. Considering the real aspects of a circuit when designing power is key for good performance as well as for EMC compliance.